SSM8405 dual enhancement mode mosfet south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , october 2007 (rev 3.0) 1 of 10 absolute maximum ra tings (t a = 25 c unless otherwise noted) paramete r symbol unit o drain-source v oltage gate-source v oltage v ds v gs 30 v 25 - + so-8 s 1 (1) -30 25 - + a drain current-continuous @ t a -pulsed drain-source diode forward current a a b i d i dm i s 7 30 1.6 w maximum power dissipation p d 2.0 o c/w c o 62.5 r ja a thermal characteristic s thermal resistance, junction-to-ambient operating junction and storage t emperature range t j , t stg -55 to 150 -4.5 -20 -1.6 n-channel limite d p-channel limite d v ds (v ) i d (a ) - 30v - 5a r ds(on ) (m ? ) max 45 @v gs = - 10v 90 @v gs = - 4.5v 1 2 3 4 5 6 7 8 g 1 (2) d 1 (7,8) d 2 (5,6) g 2 (4) s 2 (3) product summary (n-channel ) v ds (v ) i d (a ) 30v 7a r ds(on ) (m ? ) max 25 @v gs = 10v 35 @v gs = 5v product summary (p-channel ) thermal chracteristic s -5 6 1.44 o 25 c o 70 c o t a=25 c t a=70 c o 75 @v gs = - 5v 40 @v gs = 4.5v
SSM8405 south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , october 2007 (rev 3.0) 2 of 1 0 n-channel electrical characteristics (t a = 25 c unless otherwise noted) o unit symbol paramete r condition mi n ty p ma x c zero gate v oltage drain current drain-source breakdown vo ltage gate-body leakage gate threshold vo ltage drain-source on-state resistanc e bv ds s i ds s i gs s v gs(th) r ds(on) v gs =0v , i d =250 a v ds =24v , v gs =0v v gs = 25v , v ds =0v v ds =v gs ,i d =250 a v gs =10v , i d =6.6a v gs =5v , i d =5a m v v a na 30 1 100 2 25 35 1 18 28 v on-state drain current forward tr ansconductanc e tu rn-on delay t im e rise t im e tu rn-of f delay t im e fall ti me i d(on) g fs t d(on) t r t d(off) t f v ds =5v , v gs =4.5v v ds =5v , i d =6.6a v dd =15 v, v gs =10 v, 20 10 27. 5 12 7. 5 7. 5 ns p f s a input capacitanc e output capacitanc e reverse t ransfer capacitanc e c is s c oss c rs s v ds =15v v gs =0v f=1.0mhz 766 142 9 8 to tal gate charge q g v ds =15v 14 i d =6.6a, r ge n =3 1. 2 0. 8 2.3 4 v gs =0v , i d =1.6a i d =6.6a, v sd q gs q gd diode forward vo ltage gate-source charge gate-drain charge v gs =10v nc 1. 6 853 166 122 10 35 22 12 v ds =10v , i d =6.6a, v gs =10v v ds =10v , i d =6.6a, v gs =4.5v 18 6 10 4 6 v gs =4.5v , i d =5a 40 32
SSM8405 south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , october 2007 (rev 3.0) 3 of 1 0 p-channel electrical characteristics (t a = 25 c unless otherwise noted) o unit symbol parameter condition mi n ty p ma x c zero gate v oltage drain current drain-source breakdown vo ltage gate-body leakage gate threshold vo ltage drain-source on-state resistanc e bv dss i dss i gss v gs(th ) r ds(on) v gs =0v , i d = - 250 a v ds =-24v , v gs =0v v gs = 25v , v ds =0v v ds =v gs ,i d = - 250 a v gs = - 10v , i d = - 5 a v gs = - 5v , i d = - 3.5 a m v v a na - 3 0 -1 100 -2.5 45 75 -1 38 65 on-state drain current forward t ransconductanc e i d(on) g fs v ds = - 5v , v gs = - 10v v ds = - 5v , i d = - 5 a 20 10 p f s a input capacitanc e output capacitanc e reverse tr ansfer capacitanc e c is s c oss c rss v ds =-15v v gs =0v f=1.0mhz 720 155 90 -1.9 note s a. surface mounted on fr4 board, t <10 sec. b. pulse t est pulse width < 300 s, duty cycle < 2% . c. guaranteed by design, not subject to production testing. - - - 845 185 125 rise t im e fall ti me tu rn-on delay ti me tu rn-of f delay t im e to tal gate charge diode forward v oltage gate-source charge gate-drain charge t d(on) t r t d(off) t f q g v sd q gs q gd v dd = - 15v , v gs = - 10v , r l =2. 7 v ds =-15v , i d =-5a, v gs =-10v r gen =3 , v gs =0v , i d = -1.6 a i d = - 5a, v gs = -10v v ds = - 15v , v ds =-15v , i d =-5a, v gs =-4.5v 8 47 22. 5 4. 5 14 -0.8 1. 5 4. 2 7 -1.2 ns v nc 14 30 75 35 16 10 2. 8 6 gate resistanc e rg v gs =0v , v ds =0v , f=1.0mhz 3. 5 v gs = - 4.5v , i d = - 3.0 a 80 90
SSM8405 south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , october 2007 (rev 3.0 ) 4 of 1 0 v ds , drain-to-source v oltage (v ) i d ) a ( t n e r r u c n i a r d , figure 1. output characteristic s 0 2 4 6 8 10 1 2 20 16 12 8 4 0 v gs = 3v v gs = 10, 9, 8, 7, 6, 5 v v gs , gate-to-source v oltage (v ) i d ) a ( t n e r r u c n i a r d , figure 2. thansfer characteristic s 0 0.8 1.6 2.4 3.2 4.0 4.8 25 20 15 10 5 0 - 5 5 c o 25 c o tj = 125 c o v ds , drain-to-source v oltage (v ) ) f p ( e c n a t i c a p a c , c figure 3. capacitance 0 5 10 15 20 25 3 0 c i s s c r s s n-channel p-channel -v ds , drain-to-source v oltage (v ) figure 1. output characteristic s -v gs , gate-to-source v oltage (v ) i - d u c n i a r d , ) a ( t n e r r figure 2. thansfer characteristic s 0 0.5 1 1.5 2 2.5 3 25 20 15 10 5 0 - 5 5 c o 25 c o tj = 125 c o -v ds , drain-to-source v oltage (v ) ) f p ( e c n a t i c a p a c , c figure 3. capacitance 0 5 10 15 20 25 3 0 c i s s c o s s c r s s 1200 0 1000 600 400 200 800 c o s s i - d u c n i a r d , ) a ( t n e r r 0 2 4 6 8 10 1 2 20 16 12 8 4 0 -v gs = 3v -v gs = 10, 9, 8, 7, 6, 5 v v gs = 4v -v gs = 4v 1200 0 1000 600 400 200 800
SSM8405 south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , october 2007 (rev 3.0) 5 of 10 n-channel p-channel r , ) n o ( s d e c n a t s i s e r - n o ( d e z i l a m r o n ) 2.2 1.8 1.4 1.0 0.8 0.4 0.0 figure 4. on-resistance v ariation with t emperature v gs = 10v t j , junction t empertature ( c) o i d = 6.9a d e z i l a m r o n , h t v e g a t l o v d l o h s e r h t e c r u o s - e t a g tj , junction t emperature ( c) figure 5. gate threshold v ariation with t emperature o -55 -25 0 25 50 75 100 125 150 v ds = v gs i d = 250 a 1.6 1.4 1.2 1.0 0.8 0.6 0.4 v b s s d d e z i l a m r o n , e g a t l o v n w o d k a e r b e c r u o s - n i a r d figure 6. breakdown v oltage v ariation with t emperature 1.15 1.10 1.05 1.00 0.95 0.90 0.85 i d = 250 a -50 -25 0 25 50 75 100 125 150 tj , junction t emperature ( c) o r , ) n o ( s d e c n a t s i s e r - n o ( d e z i l a m r o n ) -50 0 50 100 150 1.8 1.6 1.4 1.2 1.0 0.8 0.6 figure 4. on-resistance v ariation with t emperature v gs = -10v t j , junction t empertature ( c) o v gs =-5a d e z i l a m r o n , h t v e g a t l o v d l o h s e r h t e c r u o s - e t a g tj , junction t emperature ( c) figure 5. gate threshold v ariation with t emperature o -55 -25 0 25 50 75 100 125 150 v ds = v gs i d = -250 a 1.6 1.4 1.2 1.0 0.8 0.6 0.4 v b s s d d e z i l a m r o n , g a t l o v n w o d k a e r b e c r u o s - n i a r d e figure 6. breakdown v oltage v ariation with t emperature 1.15 1.10 1.05 1.00 0.95 0.90 0.85 i d = -250 a -50 -25 0 25 50 75 100 125 150 tj , junction t emperature ( c) o -50 -25 0 25 50 75 100 125 150
SSM8405 south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , october 2007 (rev 3.0) 6 of 10 n-channel p-channel v - s g ) v ( e g a t l o v e c r u o s o t e t a g , figure 9. gate charge qg , t otal gate charge (nc) 0 3 6 9 12 15 18 21 2 4 10 8 6 4 2 0 v ds = 15v i d = 6.6 a i ds , drain-source current (a ) g , s f ) s ( e c n a t c u d n o c s n a r t figure 7. t ransconductance va riation with drain current v ds = 10v i s ) a ( t n e r r u c n i a r d - e c r u o s , v sd , body diode forward v oltage (v) figure 8. body diode forward v oltage v ariation with source current 0.4 0.6 0.8 1.0 1.2 1.4 10. 0 1.0 tj = 25 c o v - s g ) v ( e g a t l o v e c r u o s o t e t a g , figure 9. gate charge qg , t otal gate charge (nc) 10 8 6 4 2 0 v ds = -15v i d = -5 a -i ds , drain-source current (a ) g , s f ( e c n a t c u d n o c s n a r t ) s 0 5 10 15 2 0 figure 7. t ransconductance v ariation with drain current v ds = -5 v 15 12 9 6 3 0 i - s ) a ( t n e r r u c n i a r d - e c r u o s , -v sd , body diode forward vo ltage (v ) figure 8. body diode forward v oltage v ariation with source current t j = 25 c o 40. 0 0 5 10 15 2 0 v ds = 5v 15 12 9 6 3 0 10. 0 1.0 40. 0 0.4 0.6 0.8 1.0 1.2 1.4 0 3 6 9 12 15 18 21 2 4
SSM8405 south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , october 2007 (rev 3.0) 7 of 10 n-channel p-channel i d ) a ( t n e r r u c n i a r d , 0.01 v sd , drain-to-source v oltage (v) figure 10. maximum safe operating area 0.1 1 10 30 50 50 10 1 0.1 v gs = 10v single pulse t a = 25 c o r d s ( o n ) l i m i t figure 12. switching w aveforms t on t of f inver ted pulse width t r t d(on) v out v in t d(o ff ) t f 10% 50% 50% 90% 10% 90% 10% 90% i - d u c n i a r d , ) a ( t n e r r 0.01 -v sd , drain-to-source v oltage (v) figure 10. maximum safe operating area 0.1 1 10 30 50 50 10 1 0.1 v gs = -10v single pulse t a = 25 c o r d s (o n ) l i m i t figure 1 1. switching t est circuit v gs v dd r gen v out v in d r l g s 1 0 m s 1 0 0 m s 1s d c 1 0 m s 100m s 1 s d c
SSM8405 south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , october 2007 (rev 3.0 ) 8 of 1 0 n-channel figure 13. normalized thermal tr ansient impedance curv e t1 t2 p dm 1. r ja(t) = r(t)*r ja 2. r ja = see datasheet 3. t jm - t a = p dm *r ja(t) 4. duty cycle, d = t1/t2 1 10 -4 10 -3 10 -2 10 -1 10 -5 0.01 1 0.1 10 r e v i t c e f f e d e z i l a m r o n , ) t ( e c n a d e p m i l a m r e h t t n e i s n a r t duty cycle = 0.5 square w ave pulse duration (sec) 10 10 2 10 3 single pulse 0.02 0.01 0.0.5 0.2 0.1 p-channel figure 13. normalized thermal tr ansient impedance curv e t1 t2 p dm 1. r ja(t) = r(t)*r ja 2. r ja = see datasheet 3. t jm - t a = p dm *r ja(t) 4. duty cycle, d = t1/t2 1 10 -4 10 -3 10 -2 10 -1 10 -5 0.01 1 0.1 10 r e v i t c e f f e d e z i l a m r o n , ) t ( e c n a d e p m i l a m r e h t t n e i s n a r t duty cycle = 0.5 square wa ve pulse duration (sec ) 10 10 2 10 3 single pulse 0.02 0.01 0.0.5 0.1 0.2
SSM8405 package outline dimensions south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconducto r , october 2007 (rev 3.0 ) 9 of 1 0 so-8 g l c symbols millimeters inches min. max. min. max. a a1 b c d e e h l 1.35 0.069 0.053 3.99 3.81 4.98 0.41 t yp. 0.25 0.10 1.75 0.050 0.016 1.27 0.41 0.244 0.228 6.20 5.79 0.05 t yp. 1.25 t yp. 0.157 0.150 0.196 0.189 0.010 0.004 0 o 8 o o 0 o 8 1 a a1 b e 0.015 x 45 o h e d 0.20 t yp. 4.80 0.016 t yp. 0.008 t yp.
SSM8405 carrier t ape & reel dimensions south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice . south sea semiconductor , october 2007 (rev 3.0) 10 of 1 0 so- 8 p1 feeding direction p2 b0 a0 p0 d0 e1 e2 e a d1 b0 k0 package a0 b0 k0 d0 d1 e e1 e2 p0 p1 p2 t sop 8n 150 mi l 6.40 5.20 2.10 1.50 1.50 1.75 5.50 8.00 4.00 2.00 0.30 (min.) 0.10 0.30 0.05 0.05 0.05 + _ + _ + _ + uni t mm g r v w m n w1 s k h uni t mm t ape size reel siz e m n w w1 h k s g r v 330 + _ + _ + _ _ + _ + _ 12mm 330 62 1 1. 5 12. 4 0. 2 16. 8 0. 4 12.75 0.15 2. 0 0.15 0.10 _ + _ 12.00 _ _ _ _
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